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MC10H646, MC100H646 PECL/TTL-TTL 1:8 Clock Distribution Chip
Description
The MC10H/100H646 is a single supply, low skew translating 1:8 clock driver. Devices in the ON Semiconductor H646 translator series utilize the 28-lead PLCC for optimal power pinning, signal flow through and electrical performance. The single supply H646 is similar to the H643, which is a dual supply 1:8 version of the same function. The H646 was designed specifically to drive series terminated transmission lines. Special techniques were used to match the HIGH and LOW output impedances to about 7.0 W. This simplifies the choice of the termination resistor for series terminated applications. To match the HIGH and LOW output impedances, it was necessary to remove the standard IOS limiting resistor. As a result, the user should take care in preventing an output short to ground as the part will be permanently damaged. The H646 device meets all of the requirements for driving the 60 MHz and 66 MHz Intel Pentium(R) Microprocessor. The device has no PLL components, which greatly simplifies its implementation into a digital design. The eight copies of the clock allows for point-to-point clock distribution to simplify board layout and optimize signal integrity. The H646 provides differential PECL inputs for picking up LOW skew PECL clocks from the backplane and distributing it to TTL loads on a daughter board. When used in conjunction with the MC10/100E111, very low skew, very wide clock trees can be designed. In addition, a TTL level clock input is provided for flexibility. Note that only one of the inputs can be used on a single chip. For correct operation, the unused input pins should be left open. The Output Enable pin forces the outputs into a high impedance state when a logic 0 is applied. The output buffers of the H646 can drive two series terminated, 50 W transmission lines each. This capability allows the H646 to drive up to 16 different point-to-point clock loads. Refer to the Applications section for a more detailed discussion in this area. The 10H version is compatible with MECLTM 10H ECL logic levels. The 100H version is compatible with 100K levels.
Features
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PLCC-28 FN SUFFIX CASE 776
MARKING DIAGRAM*
1
MCxxxH646G AWLYYWW
xxx A WL YY WW G
= 10 or 100 = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package
*For additional marking information, refer to Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet.
* * * * * *
PECL/TTL-TTL Version of Popular ECLinPSTM E111 Low Skew Guaranteed Skew Spec Tri-State Enable Differential Internal Design VBB Output
* * * * *
Single Supply Extra TTL and ECL Power/Ground Pins Matched High and Low Output Impedance Meets Specifications Required to Drive Intel(R) Pentium(R) Microprocessors Pb-Free Packages are Available*
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
(c) Semiconductor Components Industries, LLC, 2006
November, 2006 - Rev. 5
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Publication Order Number: MC10H646/D
MC10H646, MC100H646
OGND OGND OVT Q4 Q5 Q6 Q7
Table 1. PIN DESCRIPTION
PIN EN IVT IGND VCCE VCCE VBB ECLK OGND OVT IGND IVT VEE VCCE ECLK, ECLK VBB Q0-Q7 EN FUNCTION TTL Output Ground (0 V) TTL Output VCC (+5.0 V) Internal TTL GND (0 V) Internal TTL VCC (+5.0 V) ECL VEE (0 V) ECL Ground (5.0 V) Differential Signal Input (PECL) VBB Reference Output Signal Outputs (TTL) Tri-State Enable Input (TTL)
25 Q3 OGND Q2 OVT Q1 OGND Q0 26 27 28 1 2 3 4 5 TCLK
24
23
22
21
20
19 18 17 16 15 14 13 12
6 IVT
7 IGND
8 VEE
9 VEE
10 VEE
11 ECLK Q0 Q1
Figure 1. Pinout: PLCC-28 (Top View)
EN
Table 2. TRUTH TABLE
Q2 TCLK ECLK ECLK Q4 TCLK GND GND H L X ECLK L H GND GND X ECLK H L GND GND X EN H H H H L Q L H H L Z
Q3
L = Low Voltage Level; H = High Voltage Level; Z = Tristate
Q5
Q6
Q7
Figure 2. Logic Diagram
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MC10H646, MC100H646
700 INTERNAL TTL POWER IVT01 OVT01 POWER, mW 600 500 400 300 100pF 200 OGND0 INTERNAL TTL GROUND IGND01 100 0 0 20 40 60 FREQUENCY, MHz 80 100 120 50pF No Load 200pF Power versus Frequency per Bit PDynamic = CL VSwing VCC PTotal = PStatic + PDynamic 300pF
Q0A
Figure 3. Output Structure
Figure 4. Power versus Frequency (Typical)
Table 3. 10H PECL DC CHARACTERISTICS (IVT = OVT = VCCE = 5.0 V 5%)
0C Symbol IINH IIL VIH VIL VBB Characteristic Input HIGH Current Input LOW Current Input HIGH Voltage Input LOW Voltage Output Reference Voltage IVT = IVO = VCCE = 5.0 V (Note 1) IVT = IVO = VCCE = 5.0 V (Note 1) IVT = IVO = VCCE = 5.0 V (Note 1) 0.5 3.83 3.05 3.62 4.16 3.52 3.73 Condition Min Typ Max 255 0.5 3.87 3.05 3.65 4.19 3.52 3.75 Min 25C Typ Max 175 0.5 3.94 3.05 3.69 4.28 3.555 3.81 Min 85C Typ Max 175 Unit mA mA V V V
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 1. ECL VIH, VIL and VBB are referenced to VCCE and will vary 1:1 with the power supply. The levels shown are for IVT = IVO = VCCE = 5.0 V
Table 4. 100H PECL DC CHARACTERISTICS (IVT = OVT = VCCE = 5.0 V 5%)
0C Symbol IINH IIL VIH VIL VBB Characteristic Input HIGH Current Input LOW Current Input HIGH Voltage Input LOW Voltage Output Reference Voltage IVT = IVO = VCCE = 5.0 V (Note 2) IVT = IVO = VCCE = 5.0 V (Note 2) IVT = IVO = VCCE = 5.0 V (Note 2) 0.5 3.835 3.19 3.62 4.12 3.525 3.74 Condition Min Typ Max 255 0.5 3.835 3.19 3.62 4.12 3.525 3.74 Min 25C Typ Max 175 0.5 3.835 3.19 3.62 3.835 3.525 3.74 Min 85C Typ Max 175 Unit mA mA V V V
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 2. ECL VIH, VIL and VBB are referenced to VCCE and will vary 1:1 with the power supply. The levels shown are for IVT = IVO = VCCE = 5.0 V
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MC10H646, MC100H646
Table 5. DC CHARACTERISTICS (IVT = OVT = VCCE = 5.0 V 5%)
0C Symbol VOH VOL IOS Characteristic Output HIGH Voltage Output LOW Voltage Output Short Circuit Current Condition IOH = 24 mA IOL = 48 mA (Note 3) Min 2.6 - - Max - - 0.5 - 25C Min 2.6 - - Max - - 0.5 - 85C Min 2.6 - - Max - - 0.5 - Unit V V mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 3. The outputs must not be shorted to ground, as this will result in permanent damage to the device. The high drive outputs of this device do not include a limiting IOS resistor.
Table 6. TTL DC CHARACTERISTICS (VT = VE = 5.0 V 5%)
0C Symbol VIH VIL IIH IIL VOH VOL VIK Characteristic Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current Output HIGH Voltage Output LOW Voltage Input Clamp Voltage VIN = 2.7 V VIN = 7.0 V VIN = 0.5 V IOH = -3.0 mA IOH = -24 mA IOL = 24 mA IIN = -18 mA 2.5 2.0 0.5 -1.2 Condition Min 2.0 Max 0.8 20 100 -0.6 2.5 2.0 0.5 -1.2 25C Min 2.0 Max 0.8 20 100 -0.6 2.5 2.0 0.5 -1.2 85C Min 2.0 Max 0.8 20 100 -0.6 Unit V mA mA V V V
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously.
Table 7. DC CHARACTERISTICS (IVT = OVT = VCCE = 5.0 V 5%)
0C Symbol ICCL ICCH ICCZ Characteristic Power Supply Current Condition Total all OVT, IVT, and VCCE pins Min Max 185 175 210 Min 25C Typ 166 154 Max 185 175 210 85C Min Max 185 175 210 Unit mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously.
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MC10H646, MC100H646
Table 8. AC CHARACTERISTICS (IVT = OVT = VCCE = 5.0 V 5%)
0C Symbol tPLH tPHL tSK(O) Characteristic Propagation Delay Propagation Delay Output Skew ECLK to Q TCLK to Q ECLK to Q TCLK to Q Q0, Q3, Q4, Q7 Q1, Q2, Q5 Q0-Q7 ECLK to Q TCLK to Q DtPLH - tPHL 0.3 66 MHz @ 2.0 V 66 MHz @ 0.8 V 60 MHz @ 2.0 V 60 MHz @ 0.8 V (Notes 6, 9) 5.5 5.5 6.0 6.0 $75 80 (Notes 4, 9) Condition Min 4.8 5.1 4.4 4.7 Max 5.8 6.4 5.4 6.0 350 350 500 1.0 1.3 1.0 1.5 0.3 5.5 5.5 6.0 6.0 $75 80 25C Min 5.0 5.3 4.4 4.8 Max 6.0 6.4 5.4 5.9 350 350 500 1.0 1.1 1.0 1.5 0.3 5.5 5.5 6.0 6.0 $75 80 85C Min 5.6 5.7 4.8 5.2 Max 6.6 7.0 5.8 6.5 350 350 500 1.0 1.3 1.0 1.5 Unit ns ns ps
tSK(PR) tSK(P) tr, tf tPW
Process Skew Pulse Skew Rise/Fall Time Output Pulse Width
(Notes 5, 9)
ns ns ns ns
tStability FMAX
Clock Stability Maximum Input Frequency
(Notes 7, 9) (Notes 8, 9)
ps MHz
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 4. Output skew defined for identical output transitions. 5. Process skew is valid for VCC = 5.0 V 5%. 6. Parameters guaranteed by tSK(P) and tr, tf specification limits. 7. Clock stability is the period variation between two successive rising edges. 8. For series terminated lines. See Applications section for FMAX enhancement techniques. 9. All AC specifications tested driving 50 W series terminated transmission lines at 80 MHz.
ORDERING INFORMATION
Device MC10H646FN MC10H646FNG MC10H646FNR2 MC10H646FNR2G MC100H646FN MC100H646FNG MC100H646FNR2 MC100H646FNR2G Package PLCC-28 PLCC-28 (Pb-Free) PLCC-28 PLCC-28 (Pb-Free) PLCC-28 PLCC-28 (Pb-Free) PLCC-28 PLCC-28 (Pb-Free) Shipping 37 Units / Rail 37 Units / Rail 500 / Tape & Reel 500 / Tape & Reel 37 Units / Rail 37 Units / Rail 500 / Tape & Reel 500 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
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MC10H646, MC100H646
Resource Reference of Application Notes
AN1405/D AN1406/D AN1503/D AN1504/D AN1568/D AN1672/D AND8001/D AND8002/D AND8020/D AND8066/D AND8090/D - ECL Clock Distribution Techniques - Designing with PECL (ECL at +5.0 V) - ECLinPSt I/O SPiCE Modeling Kit - Metastability and the ECLinPS Family - Interfacing Between LVDS and ECL - The ECL Translator Guide - Odd Number Counters Design - Marking and Date Codes - Termination of ECL Logic Devices - Interfacing with ECLinPS - AC Characteristics of ECL Devices
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MC10H646, MC100H646
PACKAGE DIMENSIONS
PLCC-28 FN SUFFIX PLASTIC PLCC PACKAGE CASE 776-02 ISSUE E
Y BRK D Z -L- -M- B 0.007 (0.180) U
M
T L-M
M
S
N
S S
-N-
0.007 (0.180)
T L-M
N
S
W
28 1
D
V
X VIEW D-D
G1
0.010 (0.250)
S
T L-M
S
N
S
A Z R E G G1 0.010 (0.250)
S
0.007 (0.180) 0.007 (0.180)
M M
T L-M T L-M
S S
N N
S S
H
0.007 (0.180)
M
T L-M
S
N
S
C
K1 0.004 (0.100) -T- SEATING
PLANE
J
K F VIEW S 0.007 (0.180)
M
VIEW S T L-M
S
T L-M
S
N
S
N
S
NOTES: 1. DATUMS -L-, -M-, AND -N- DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM -T-, SEATING PLANE. 3. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635).
DIM A B C E F G H J K R U V W X Y Z G1 K1
INCHES MIN MAX 0.485 0.495 0.485 0.495 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 --- 0.025 --- 0.450 0.456 0.450 0.456 0.042 0.048 0.042 0.048 0.042 0.056 --- 0.020 2_ 10_ 0.410 0.430 0.040 ---
MILLIMETERS MIN MAX 12.32 12.57 12.32 12.57 4.20 4.57 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 0.51 --- 0.64 --- 11.43 11.58 11.43 11.58 1.07 1.21 1.07 1.21 1.07 1.42 --- 0.50 2_ 10_ 10.42 10.92 1.02 ---
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MC10H646, MC100H646
ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC). MECL 10H is a trademark of Motorola, Inc. Pentium is a registered trademark of Intel Corporation.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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MC10H646/D

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